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Features
* Low-voltage and Standard-voltage Operation * * * * * * * * * *
- 2.7 (VCC = 2.7V to 5.5V) - 1.8 (VCC = 1.8V to 5.5V) User Selectable Internal Organization - 16K: 2048 x 8 or 1024 x 16 Three-wire Serial Interface Sequential Read Operation Schmitt Trigger, Filtered Inputs for Noise Suppression 2 MHz Clock Rate (5V) Compatibility Self-timed Write Cycle (10 ms max) High Reliability - Endurance: 1 Million Write Cycles - Data Retention: 100 Years Automotive Devices Available 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), and 8lead TSSOP Packages Die Sales: Wafer Form, Waffle Pack and Bumped Wafers
Three-wire Serial EEPROM
16K (2048 x 8 or 1024 x 16)
Description
The AT93C86A provides 16384 bits of serial electrically erasable programmable read only memory (EEPROM), organized as 1024 words of 16 bits each when the ORG pin is connected to VCC and 2048 words of eight bits each when it is tied to ground. The device is optimized for use in many industrial and commercial applications where lowpower and low-voltage operations are essential. The AT93C86A is available in space saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), and 8lead TSSOP packages.
AT93C86A
Table 1. Pin Configurations
Pin Name CS SK DI DO GND VCC ORG NC Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Supply Internal Organization No Connect 8-lead Ultra Thin Mini-MAP (MLP 2x3)
VCC NC ORG GND
8 7 6 5
8-lead PDIP
CS SK DI DO 1 2 3 4 8 7 6 5 VCC NC ORG GND
8-lead SOIC
CS SK DI DO 1 2 3 4 8 7 6 5 VCC NC ORG GND
8-lead TSSOP
CS SK DI DO 1 2 3 4 8 7 6 5 VCC NC ORG GND
CS SK 3 DI 4 DO
1 2
Bottom View
Rev. 3408H-SEEPR-1/07
1
The AT93C86A is enabled through the Chip Select pin (CS), and accessed via a threewire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK). Upon receiving a Read instruction at DI, the address is decoded and the data is clocked out serially on the data output pin DO. The Write cycle is completely self-timed and no separate Erase cycle is required before Write. The Write cycle is only enabled when the part is in the Erase/Write Enable state. When CS is brought "high" following the initiation of a Write cycle, the DO pin outputs the Ready/Busy status of the part. The AT93C86A is available in a 2.7V to 5.5V version.
Absolute Maximum Ratings*
Operating Temperature......................................-55C to +125C Storage Temperature .........................................-65C to +150C Voltage on any Pin with Respect to Ground ........................................ -1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
Figure 1. Block Diagram
Vcc GND
MEMORY ARRAY ORG 2048 x 8 OR 1024 x 16 ADDRESS DECODER
DATA REGISTER DI MODE DECODE LOGIC OUTPUT BUFFER
CS
SK
CLOCK GENERATOR
DO
Note:
When the ORG pin is connected to Vcc, the x 16 organization is selected. When it is connected to ground, the x 8 organization is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the internal 1 Meg ohm pullup, then the x 16 organization is selected.
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AT93C86A
Table 2. Pin Capacitance(1) Applicable over recommended operating range from TA = 25C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Symbol COUT CIN Note: Test Conditions Output Capacitance (DO) Input Capacitance (CS, SK, DI) 1. This parameter is characterized and is not 100% tested. Max 5 5 Units pF pF Conditions VOUT = 0V VIN = 0V
Table 3. DC Characteristics Applicable over recommended operating range from: TAI = -40C to +85C, VCC = +1.8V to +5.5V, TAE = -40C to +125C, VCC = +1.8V to +5.5V (unless otherwise noted)
Symbol VCC1 VCC2 VCC3 ICC ISB1 ISB2 ISB3 IIL IOL VIL1(1) VIH1(1) VIL2(1) VIH2(1) VOL1 VOH1 VOL2 VOH2 Note: Parameter Supply Voltage Supply Voltage Supply Voltage Supply Current Standby Current Standby Current Standby Current Input Leakage Output Leakage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage VCC = 5.0V VCC = 1.8V VCC = 2.7V VCC = 5.0V VIN = 0V to VCC VIN = 0V to VCC 2.7V VCC 5.5V 1.8V VCC 2.7V 2.7V VCC 5.5V 1.8V VCC 2.7V IOL = 2.1 mA IOH = -0.4 mA IOL = 0.15 mA IOH = -100 A VCC - 0.2 2.4 0.2 ---0.6 2.0 -0.6 VCC x 0.7 READ at 1.0 MHz WRITE at 1.0 MHz CS = 0V CS = 0V CS = 0V Test Condition Min 1.8 2.7 4.5 0.5 0.5 0 6.0 17 0.1 0.1 Typ Max 5.5 5.5 5.5 2.0 2.0 0.1 10.0 30 3.0 3.0 0.8 VCC + 1 VCC x 0.3 VCC + 1 0.4 Unit V V V mA mA A A A A A V V V V V V
1. VIL min and VIH max are reference only and are not tested.
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Table 4. AC Characteristics Applicable over recommended operating range from TAI = -40C to + 85C, TAE = -40C to +125C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol fSK Parameter SK Clock Frequency SK High Time SK Low Time Minimum CS Low Time CS Setup Time DI Setup Time CS Hold Time DI Hold Time Output Delay to "1" Output Delay to "0" CS to Status Valid CS to DO in High Impedance Write Cycle Time
(1)
Test Condition 4.5V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V Relative to SK Relative to SK Relative to SK Relative to SK AC Test AC Test AC Test AC Test CS = VIL 2.7V VCC 5.5V 1.8V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V 1.8V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V 2.7V VCC 5.5V 1.8V VCC 5.5V
Min 0 0 0 250 1000 250 1000 250 1000 50 200 100 400 0 100 400
Typ
Max 2 1 0.25
Units MHz
tSKH tSKL tCS tCSS tDIS tCSH tDIH tPD1 tPD0 tSV tDF tWP Endurance
ns ns ns ns ns ns ns 250 1000 250 1000 250 1000 150 400 ns ns ns ns ms ms
0.1
3
10
5.0V, 25C
1M
Write Cycles
Note:
1. This parameter is ensured by characterization.
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Table 5. Instruction Set for the AT93C86A
Address Instruction READ EWEN ERASE WRITE ERAL WRAL SB 1 1 1 1 1 1 Op Code 10 00 11 01 00 00 x8 A10 - A0 11XXXXXXXXX A10 - A0 A10 - A0 10XXXXXXXXX 01XXXXXXXXX x 16 A9 - A0 11XXXXXXXX A9 - A0 A9 - A0 10XXXXXXXX 01XXXXXXXX D7 - D0 D15 - D0 D7 - D0 D15 - D0 x8 Data x 16 Comments Reads data stored in memory, at specified address. Write enable must precede all programming modes. Erases memory location An - A0. Writes memory location An - A0. Erases all memory locations. Valid only at VCC = 4.5V to 5.5V. Writes all memory locations. Valid when VCC = 4.5V to 5.5V and Disable Register cleared. Disables all programming instructions.
EWDS
1
00
00XXXXXXXXX
00XXXXXXXX
Functional Description
The AT93C86A is accessed via a simple and versatile three-wire serial communication interface. Device operation is controlled by seven instructions issued by the host processor. A valid instruction starts with a rising edge of CS and consists of a Start Bit (logic "1") followed by the appropriate Op Code and the desired memory address location. READ (READ): The Read (READ) instruction contains the address code for the memory location to be read. After the instruction and address are decoded, data from the selected memory location is available at the serial output pin DO. Output data changes are synchronized with the rising edges of serial clock SK. It should be noted that a dummy bit (logic "0") precedes the 8- or 16-bit data output string. The AT93C86A supports sequential read operations. The device will automatically increment the internal address pointer and clock out the next memory location as long as CS is held high. In this case, the dummy bit (logic "0") will not be clocked out between memory locations, thus allowing for a continuous stream of data to be read. ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN) instruction must be executed first before any programming instructions can be carried out. Please note that once in the EWEN state, programming remains enabled until an EWDS instruction is executed or VCC power is removed from the part. ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified memory location to the logical "1" state. The self-timed erase cycle starts once the ERASE instruction and address are decoded. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A logic "1" at pin DO indicates that the selected memory location has been erased, and the part is ready for another instruction. WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be written into the specified memory location. The self-timed programming cycle tWP starts after the last bit of data is received at serial data input pin DI. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of
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250 ns (tCS). A logic "0" at DO indicates that programming is still in progress. A logic "1" indicates that the memory location at the specified address has been written with the data pattern contained in the instruction and the part is ready for further instructions. A Ready/Busy status cannot be obtained if the CS is brought high after the end of the selftimed programming cycle tWP. ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array to the logic "1" state and is primarily used for testing purposes. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V 10%. WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the instruction. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). The WRAL instruction is valid only at VCC = 5.0V 10%. ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturbance, the Erase/Write Disable (EWDS) instruction disables all programming modes and should be executed after all programming operations. The operation of the READ instruction is independent of both the EWEN and EWDS instructions and can be executed at any time.
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AT93C86A
Timing Diagrams
Figure 2. Synchronous Data Timing
Note:
1. This is the minimum SK period.
Organization Key for Timing Diagrams
AT93C86A (16K) I/O AN DN x8 A10 D7 x 16 A9 D15
Figure 3. READ Timing
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Figure 4. EWEN Timing
CS
tCS
SK
DI
1
0
0
1
1
...
Figure 5. EWDS Timing
CS
tCS
SK
DI
1
0
0
0
0
...
Figure 6. WRITE Timing
CS
tCS
SK
DI
1
0
1
AN
...
A0
DN
...
D0
DO
HIGH IMPEDANCE
BUSY
READY
tWP
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AT93C86A
Figure 7. WRAL Timing(1)
CS
tCS
SK
DI
1
0
0
0
1
...
DN
...
D0
DO
HIGH IMPEDANCE
BUSY READY
tWP
Note: 1. Valid only at VCC = 4.5V to 5.5V.
Figure 8. ERASE Timing
tCS CS
CHECK STATUS STANDBY
SK
DI
1
1
1
AN AN-1 AN-2
...
A0 tSV tDF
HIGH IMPEDANCE READY
DO
HIGH IMPEDANCE
BUSY
tWP
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Figure 9. ERAL Timing(1)
Note:
1. Valid only at VCC = 4.5V to 5.5V.
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AT93C86A
AT93C86A Ordering Information(1)
Ordering Code AT93C86A-10PU-2.7 AT93C86A-10PU-1.8(2) AT93C86A-10SU-2.7(2) AT93C86A-10SU-1.8(2) AT93C86A-10TU-2.7(2) AT93C86A-10TU-1.8(2) AT93C86AY1-10YU-1.8(2)(Not recommended for new design) AT93C86AY6-10YH-1.8(3) AT93C86A-W1.8-11(4) Notes: 1. 2. 3. 4.
(2)
Package 8P3 8P3 8S1 8S1 8A2 8A2 8Y1 8Y6 Die Sale
Operation Range
Lead-Free/Halogen-Free/ Industrial Temperature (-40C to 85C)
Industrial Temperature (-40C to 85C)
For 2.7V devices used in a 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables. "U" designates Green package + RoHS compliant. "H" designates Green Package + RoHS compliant, with NiPdAu Lead Finish. Available in Waffle pack and Wafer form; order as SL788 for inkless Wafer form. Bumped die available upon request. Please contact Serial EEPROM marketing.
Package Type 8P3 8S1 8A2 8Y1 8Y6 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP) 8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm) Options -2.7 -1.8 Low Voltage (2.7V to 5.5V) Low Voltage (1.8V to 5.5V)
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Packaging Information
8P3 - PDIP
E E1
1
N
Top View
c eA
End View
D e D1 A2 A
SYMBOL
COMMON DIMENSIONS (Unit of Measure = inches) MIN NOM MAX NOTE
A A2 b b2 b3 c D 0.115 0.014 0.045 0.030 0.008 0.355 0.005 0.300 0.240 0.310 0.250 0.100 BSC 0.300 BSC 0.115 0.130 0.130 0.018 0.060 0.039 0.010 0.365
0.210 0.195 0.022 0.070 0.045 0.014 0.400
2
5 6 6
3 3
b2 b3
4 PLCS
L
D1 E E1 e eA L
b
0.325 0.280
4 3
Side View
4 0.150 2
Notes:
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. 8P3 REV. B
R
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AT93C86A
8Y6 - MLP 2x3 mm
A
D2
b (8X)
Pin 1 Index Area E2 E
Pin 1 ID L (8X)
D A2 A3 A1
e (6X) 1.50 REF.
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL D E D2 E2 A A1 A2 A3 L e b 0.20 0.20 1.40 0.0 MIN NOM 2.00 BSC 3.00 BSC 1.50 0.02 0.20 REF 0.30 0.50 BSC 0.25 0.30 2 0.40 1.60 1.40 0.60 0.05 0.55 MAX NOTE
Notes:
1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions, tolerances, datums, etc. 2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.
8/26/05 2325 Orchard Parkway San Jose, CA 95131 DRAWING NO. TITLE 8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map, 8Y6 Dual No Lead Package (DFN) ,(MLP 2x3) REV. C
R
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8S1 - JEDEC SOIC
C
1
E
E1
N
L
Top View End View
e B A
SYMBOL COMMON DIMENSIONS (Unit of Measure = mm) MIN 1.35 0.10 0.31 0.17 4.80 3.81 5.79 NOM - - - - - - - 1.27 BSC 0.40 0 - - 1.27 8 MAX 1.75 0.25 0.51 0.25 5.00 3.99 6.20 NOTE
A1
A A1 B C
D
D E1 E
Side View
e L
Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. 8S1 REV. B
R
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AT93C86A
8A2 - TSSOP
3 21
Pin 1 indicator this corner
E1
E
L1
N L
Top View
End View
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 2.90 NOM 3.00 6.40 BSC 4.30 - 0.80 0.19 4.40 - 1.00 - 0.65 BSC 0.45 0.60 1.00 REF 0.75 4.50 1.20 1.05 0.30 4 3, 5 MAX 3.10 NOTE 2, 5
b
A
D E E1 A
e D
A2
A2 b e
Side View
L L1
Notes:
1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 5/30/02
R
2325 Orchard Parkway San Jose, CA 95131
TITLE 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
DRAWING NO. 8A2
REV. B
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8Y1 - MAP
PIN 1 INDEX AREA
A 1 2 3 4
PIN 1 INDEX AREA
E1 D D1
L 8 E A1 b 7 6 5 e
Top View
End View
Bottom View
COMMON DIMENSIONS (Unit of Measure = mm)
SYMBOL
A
A A1
MIN - 0.00 4.70 2.80 0.85 0.85 0.25
NOM - - 4.90 3.00 1.00 1.00 0.30 0.65 TYP
MAX 0.90 0.05 5.10 3.20 1.15 1.15 0.35
NOTE
Side View
D E D1 E1 b e L
0.50
0.60
0.70
2/28/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package (MAP) Y1 DRAWING NO. 8Y1 REV. C
R
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Revision History
Doc. Rev. 3408H 3408G
Date 1/2007 7/2006
Comments Add "Bottom View" to pg 1 Ultra Thin MiniMap package drawing pg 4 revise Note 1 added "ensured by characterization" Revision history implemented. Deleted `Preliminary' status from datasheet; Added `Ultra Thin' description to MLP 2x3 package; Deleted `1.8V not available' on Figure 1 Note; Added 1.8V range on Table 4 under Write Cycle Time.
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3408H-SEEPR-1/07

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